Dynamic Cache Reconfiguration For Energy Optimization In Chip Multiprocessors
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Cache reconfiguration for chip multiprocessors (CMP) in order to reduce energy consumption is a challenging research problem. This thesis presents a dynamic scheme for level one cache design where the processing core can dynamically switch to a lower energy configuration. The proposed scheme is based on a heuristic that can either be executed as part of the firmware or implemented in hardware with very low additional overhead. The heuristic functions periodically after a pre-defined fixed interval for each processing core. The heuristic first examines the statistics calculated over the previous intervals and then switches the cache to an improved configuration if it can lead to energy savings. We evaluate our approach extensively by testing benchmarks from the PARSEC 2.1, MiBench and SPLASH-2 benchmark suites on a simulated 4-core CMP using a modified Multi2Sim 3.2.1 simulator. The results indicate that the proposed scheme provides on average 16.92% savings in energy consumption with only a 3.01% reduction in instructions per cycle as compared to a regular 16KB 4-way L1 cache.