A COMPARATIVE STUDY OF THE THERMO-MECHANICAL BEHAVIOR OF WCSP ASSEMBLY DUE TO DIFFERENCE IN PCBS’ LAYER THICKNESS

Abstract

The reliability of Chip Scale Package assembly is of great concern for the electronic industry. Due to multiple function integration of the present devices there is a high demand of ultra-miniaturization of the integrated parts to build the inside circuit assembly. Wafer Level Chip Scale Packages (WLCSP) are used in the industry to meet the challenges of these miniaturization due to its form factor, not so high cost and packaging efficiency which is also very high despite the known and unknown reliability issues. WLSCPs use packaging technology at the wafer level which is an extension of the wafer fab process where the final device is a die with an array pattern of solder interconnects. This WLCSP stands out from the regular Ball Grid Array (BGA) and laminate based Chip Scale Packages as there are no bond wires or interposer used for connections, but WLCSP has issues which makes the solder life short and so concerning ourselves with their reliability should be our prime concern. In the whole assembly a crucial part of reliability is played by the Printed Circuit Boards (PCB) which is a multi-layered structure. During Thermal cycling test, stress is accumulated in the solders due to mismatch of coefficient of thermal expansion (CTE) between the PCB and the package. In a PCB there are multiple layers and on their own possess different material properties and overall has effect on the properties of the board itself which is by nature orthotropic. So significant warpage also occurs in PCB which has an effect on the solder joints. By removing the layers or through different composition of the layers of the PCB changes the material properties of the board. It affects the life of the solder balls either in a good way or a bad way. The primary objective of this work is to make an effort to look into the possible effects of individual layers during thermal cycling and thermal shock, to see the effect of ramp and dwell time on the WCSP assembly by considering layer removal from the PCBs, thus changing the overall thickness of the boards.