| dc.contributor.advisor | Johnson, Taylor | |
| dc.creator | Long, Randy Kyle | |
| dc.date.accessioned | 2016-10-25T19:44:30Z | |
| dc.date.available | 2016-10-25T19:44:30Z | |
| dc.date.created | 2016-08 | |
| dc.date.issued | 2016-08-26 | |
| dc.date.submitted | August 2016 | |
| dc.identifier.uri | http://hdl.handle.net/10106/26134 | |
| dc.description.abstract | This document presents a design method and example for a time-triggered CAN (TTCAN) system which reduces latency, variability in transmission frequency, and increases data throughput relative to the traditional free-for-all CAN (FFACAN) transmission system.
In addition to performance considerations for a TTCAN transmission scheme, this document also presents a simple method for measuring CPU usage on embedded systems that use either nested or non-nested interrupts. Systems that use non-nested interrupts may have their performance measured with a single GPIO pin; systems that use nested interrupts require one pin per interrupt service routine. | |
| dc.format.mimetype | application/pdf | |
| dc.subject | Controller area networks | |
| dc.subject | Time division multiple access | |
| dc.subject | Formula SAE | |
| dc.subject | CPU performance | |
| dc.subject | CAN | |
| dc.subject | TDMA | |
| dc.subject | FSAE | |
| dc.title | Time-Triggered Controller Area Network Design for Formula SAE Racecars and Technique for Measuring CPU Usage on Systems with Nested and Non-Nested Interrupts | |
| dc.type | Thesis | |
| dc.degree.department | Electrical Engineering | |
| dc.degree.name | Master of Science in Electrical Engineering | |
| dc.date.updated | 2016-10-25T19:45:01Z | |
| thesis.degree.department | Electrical Engineering | |
| thesis.degree.grantor | The University of Texas at Arlington | |
| thesis.degree.level | Masters | |
| thesis.degree.name | Master of Science in Electrical Engineering | |
| dc.type.material | text | |
| dc.creator.orcid | 0000-0002-0579-2110 | |
