STRUCTURAL OPTIMIZATION & RELIABILITY OF 3D PACKAGE BY STUDYING CRACK BEHAVIOR ON TSV & BEOL & IMPACT OF POWER CYCLING ON RELIABILITY FLIP CHIP PACKAGE
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The 3D packaging is stacked of chips on top of another which is emerging as a powerful technology that satisfies such integrated circuit (IC) package demands. Most of the stress develops at interfaces and the interface delamination of TSV may encounter which is mainly driven by a shear stress concentration at the point. In this study, the effect of package structure on the failure metric of the 3D package has been studied. J-integral has been used to quantify the crack driving force. The crack is modeled at the TSV and BEOL (Back End of the Line) and the die -substrate thickness is varied and studied during the chip attachment process and under Accelerated Thermal Cycling (ATC) load for optimizing the value of die and substrate thickness. Finite Element methods have been used to analyze the thermo-mechanical stresses and fracture parameters in TSV structures 3D package. An optimized package structure was obtained to reduce the crack driving energy in the TSV region and in the BEOL dielectric layer. An effort is made to understand the mechanism of the effect of number & thicknesses of cores, FR4 and Cu layers on the substrate has been studied through finite element analysis of mechanical interaction at the Si/TSV regions, back-end Cu/low-k stack, and the inter-die µ-bumps during chip attachment. Analyzed that PCB stack up significantly affect the fatigue life under Thermal cycling, thermal shock & reflow condition. The second half of the thesis includes research on Ball Grid Array Package (BGA) which gained popularity among the industry due to its low cost, compact size, and excellent thermal electrical performance characteristics. When an electronic device is turned off and then turned on multiple times, it creates a loading condition called power cycling. The solder joint reliability assessment of BGA is done through computational method i.e. Finite element analysis (FEA) under two different loads. In this work, the power cycling and thermal cycling act as a combined load. Three different BGA boards were used for analysis and comparison has been done to investigate the impact of thickness and copper content of board on solder joint reliability under power cycling and thermal cycling. The mismatch in CTE between components used in BGA and the non-uniform temperature distribution makes the package deform differently. Modeling of life prediction is usually conducted for ATC condition, which assumes uniform temperature throughout the assembly.