Flip Chip Back End Design Parameters To Reduce Bump Electromigration

Abstract

The advancement in flip chip technology has enabled us to meet the requirement of smaller die size along with the increased functionality. Due to this development in flip chip packaging technology along with higher current carrying requirement of solder bumps, electromigration has now become a reliability concern. In this research, a commercially available finite element tool is adopted in order to study the distribution of current density in eutectic solder bump for variety of back end design parameters. Geometries needed were generated by using Pro/Engineer® Wildfire 3.0 as a Computer-Aided-Design (CAD) tool and were transferred to ANSYS® 10.0, where meshed analysis was conducted. Parameters such as passivation opening (PO) diameter, trace width, under bump metallurgy (UBM) thickness and UBM diameter were studied in detail. The results were evaluated for input currents of 0.1 A and 0.5 A. Based on the results, a guideline for solder bump configuration is proposed. In the metallization, the most important design attribute found is the Al trace width. In the metallization of the structures used in our study, current density varied from 5x105 A/cm2 to 7x105 A/cm2 and from 2.5x106 A/cm2 to 3.5x106 A/cm2 at 0.1 and 0.5 A per bump, respectively. In the solder bump, the most important parameters found are Al trace width and UBM thickness. In the solder of the structures used in our study, current density varied from 2.8x103 A/cm2 to 4.2x104 A/cm2 and from 1.4x104 and 2.1x105 A/cm2 at 0.1 and 0.5 A per bump, respectively. Simulation was done to show the effect of stress on passivation opening of the solder bump. Results show that bumps with small PO diameter show higher stress levels. Also, maximum stress is noted at the same location where current crowding occurs.