Assessment Of The Mechanical Integrity Of Cu/low-k Dielectric In A Flip Chip Package

Abstract

Miniaturization and more recently convergence have been driving the industry since the invention of the transistor and integrated circuit (IC). Though the gate delay has decreased with transistor scaling, the increase in the resistive capacitive (RC) interconnect delay due to shrinking interconnect dimensions has become a serious concern for the development of future-generation electronics. To reduce the delay due to resistance R, a major technology change was the replacement of Aluminum (Al) with Copper (Cu) interconnect layers in the BEoL (Back-end-of-line). Recently, some investigators have suggested using low-k dielectric (having dielectric constant less than 4) instead of SiO2 (k= 3.9) to reduce the capacitive component in the RC delay. Low-k dielectric materials have characteristics such as low mechanical strength, hardness and adhesion, thereby making it imperative to characterize their thermo-mechanical response. Integration of Cu/low-k interconnects has become a critical reliability issue from the foundry's standpoint as well as package reliability. The thermo-mechanical stresses are induced inside the chip during various fabrication processes, field use, etc. The CTE mismatch between the various components leads to significant warpage and stresses in the metal/dielectric region of the die. Very little work in this area has been done for metal/dielectric stability. In this study, a 3-D multi-level finite element (MLFE) approach has been used to examine the mechanical integrity of the Nano-scale inter-layer-dielectric (ILD) when the package is subjected to thermal shock. Since thickness of each layer in the metal/dielectric region is few orders of magnitude lower than that of the chip/substrate (at least 3 orders) it is almost impossible to analyze it at the global level. Therefore, sub-modeling technique has been leveraged to conduct a relatively accurate estimation of the mechanical behavior of the Cu/low-k region under thermal shock condition. A comparative analysis of the mechanical response of the Cu/low-k region is done for 2 cases - 1) ILD taken as linear material (commonly used industry practice to save computational time) 2) temperature dependent non-linearity of the ILD is implemented and creep and plastic response is captured. The creep model was implemented to represent its realistic mechanical behavior. This study demonstrates the variation in the thermo-mechanical response between the 2 cases thereby addressing the importance of a non-linear analysis for such systems. The developed framework is further utilized to perform a parametric analysis for the number of BEoL layers and to study the effect of underfill properties on the structural integrity of the dielectric layers. Further the model is parameterized to study the effect of the die thickness and the number of interconnect layers in a flip chip package.