Browsing Theses and Dissertations(library) by Subject "Wafer-level chip scale packages"
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Study of SAC Solder Interconnect Parameters in Microelectronic Semiconductor Packaging and their Effects on Electromigration Failure Mechanisms
(2021-12-13)As the shrinkage of electronic devices becomes more appealing, so do their high capacity and efficiency. This demand for ever-shrinking sizes of electronic devices follows the trend predicted by Moore’s Law. To achieve ...