3D Interconnects For Die And Wafer Stacks
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3D integration results from the ever demanding trend towards smaller and lower-profile, lighter and lower cost packaged devices requires further package miniaturization. With the present System-on-chip (SOC) technology reaching its limitation in terms of functionality and cost, effort are being concentrated on exploring the third dimension, i.e. 3D integration. It provides a volumetric packaging solution for higher integration and performance and results in size and weight reduction. Approaches to achieve 3D integration are die and wafer stacking. A key technology to realize the potential of stacking is implementation of vertical electrical interconnects between die and wafer stacks. This thesis discusses the approach to form vertical interconnects between wafer stacks through solder reflow. It elaborates the fabrication process for formation of electrical interconnects and wafer bonding using photosensitive Benzocyclobutene (BCB). Profiler results of solder reflow are also included. Die level bonding for die stacking is also discussed. Bonding is achieved using a fluxless soldering and electrical interconnections between dies are formed through thermo-compression bonding. Two different solder compositions were used and bonding results are discussed. Furthermore, low frequency and high frequency analysis of interconnects are done to select the correct dimension for interconnects specific to the application.