Power-Derived Thermal Characterization of SiGe HBTs and Design of Timing Circuit using a Phase Locked-Loop

Abstract

Silicon Germanium (SiGe) hetero-junction bipolar transistors (HBTs) have been designed to cater the demand of high speed circuits having speed applications in wireless, optical communication and space electronics. Due to higher cut-off frequencies and high speed applications, self heating plays a significant role in the performance of SiGe HBTs. This dissertation paper does an extensive analysis on the effect of self heating and used DC measurement methods to extract the self heating parameter, thermal resistance (Rth). A non-linear thermal model is proposed to take into account the effects of the non-linearity in device parameters with increase in device temperature. The HICUM (HIgh CUrrent Model) model is used for all the simulations. Simulations are performed using IC-CAP (Integrated Circuit Characterization and Analysis Program) tool. The linear thermal model attached at the thermal node of the HICUM model was replaced with a Current Controlled Voltage Source (CCVS) in order to implement the non-linear thermal model for simulations. Measurements are done using HP 4142B modular DC source/module connected to the computer via Hewlett-Packard Interface Bus (HPIB). Texas Instruments, Incorporation’s SiGe LV (Low Voltage) HBTs with varying emitter lengths are used for measurements. The second project of this research is to design a timing circuit with an output jitter of the order of ~ 5 ps. The timing circuit was designed using a Phase Locked Loop (PLL). The basic concept of this system is based on the similar system designed at Stanford Linear Accelerator (SLAC). The input reference signal is provided by the Timing, Trigger and Control (TTC) Systems for the Large Hadron Collider (LHC) at Conseil Europeen por la Recherche Nucleaire (CERN). The frequency of the reference signal is ~ 40 MHz. Jitter content of this signal prevents it to be used as a timing signal for other electronics. In order to re-use the basic design from SLAC, this reference signal is up-converted to ~ 480 MHz using a two step up-conversion process. This up-converted signal is then stabilized using a PLL. After stabilization (jitter reduction) the 480 MHz signal is down-converted using a divider with division factor of 12. The jitter in the final output signal is of the order of ~ 2 ps.