STUDY OF CRACK PROPAGATION UNDER THERMAL LOADING ON A 3D TSV PACKAGE

Abstract

Today, there is a revolution in going for miniaturization in size of electronic packages. More thinner, lighter and complex packages are in use for almost every electronic device. This initiation was taken to the next level and gives us a whole new ideology called 3D packaging. Currently, 3D packaging is the on-going research in almost all the electronic packaging related industries. 3D package uses Through Silicon Via (TSV) technology that gained momentum in the development and helped packaging system for significant miniaturization and power reduction, which result in increased performance. However, the reliability assessment is needed to evaluate the critical areas in TSV based 3D ICs. In electronic packages, reliability is the most important issue for electronic device manufacturing company and in any research institutes. In this paper, the different types of crack that can happen along the TSV/Si interface has been determined with the study of behaviors of crack. Finite element method is used for the analysis of TSV region and calculation of stress intensity factor (SIF). Stress Intensity Factor (SIF) is a function of applied load, component dimensions and the length of the crack. Analyzing all these functions will help us to give more ideas about crack propagation and thereby help us to take preventive measures.