THERMAL MODELING OF 3-DIMENSIONALLY STACKED DRAM MEMORY

Abstract

A large fraction of energy consumed in modern microelectronic devices and systems is taken up by memory access operations, which is expected to cause significant temperature rise. Since memory access operations are very short this is expected to inherently be a transient thermal phenomenon. Despite the critical importance of thermal management in microelectronics, not much work exists on understanding the nature of thermal transport during memory access operations. In this work, a mathematical model to predict the transient temperature rise within a 3D layered memory chip is presented. Most heat-generating memory access processes occur over a short timescale for which the thermal penetration depth is shorter than the die thickness. This enables the modeling of such processes independent of the nature of the chip cooling by treating the chip as a combination of semi-infinite and infinite medium layered bodies. A semi-infinite Green's function model is developed for topmost layer of memory. The subsequent layers: 2 to n layers have been modeled on a thermally infinite layer concept. This model is validated against finite element simulation results. The analytical model is used to analyze transient thermal effects of various memory access processes for multiple banks. Finally, a thermal simulator based on 4 layers of memory is presented which shows the capability of any input sequence of operation along the x,y,z,t directions and resulting temperature rise due to its access. This is used as a limiting case to show that the maximum number of accesses that can be performed on a 4-layered structure where each layer consists of 10x10 grid, i.e. 400 cells. These result will help develop an understanding of optimal layouts and processes for 3D memory chips, eventually leading to co-design tools that simultaneously improve thermal and electrical performance of 3D memory chips.