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dc.contributor.author | Ju, Miao | en_US |
dc.date.accessioned | 2011-10-11T20:48:48Z | |
dc.date.available | 2011-10-11T20:48:48Z | |
dc.date.issued | 2011-10-11 | |
dc.date.submitted | January 2011 | en_US |
dc.identifier.other | DISS-11294 | en_US |
dc.identifier.uri | http://hdl.handle.net/10106/6177 | |
dc.description.abstract | With ever expanding design space and workload space in multicore era, a key challenge to program a multithreaded multicore processor is how to evaluate the performance of various possible program-task-to-core mapping choices and provide effective resource allocation during the initial programming phase, when the executable program is yet to be developed. In this dissertation, we put forward a thread-level modeling methodology to meet this challenge. The idea is to model thread-level activities only and overlook the instruction-level and microarchitectural details. A model developed at this level assumes the availability of only a piece of pseudo code that contains information about the thread-level activities, rather than an executable program that provides instruction-by-instruction information. Moreover, since the thread-level modeling is much coarser than the instruction-level modeling, the analysis at this level turns out to be significantly faster than that at the instruction level.\\ The above features make the methodology particularly amenable for fast performance evaluation of a large number of program-task-to-core mapping choices during the initial programming phase. Based on this methodology, in this dissertation we further developed: 1) an analytic modeling technique based on queuing theory which allows large design space exploration; and 2) a framework that allows program tasks to be mapped to different core resources to achieve maximal throughput performance for many-core processors. Case studies against cycle-accurate simulation demonstrate that the throughput estimated using our modeling technique is consistently within 8\% of cycle-accurate simulation results. | en_US |
dc.description.sponsorship | Che, Hao | en_US |
dc.language.iso | en | en_US |
dc.publisher | Computer Science & Engineering | en_US |
dc.title | Performance Analysis And Resource Allocation For Multithreaded Multicore Processors | en_US |
dc.type | Ph.D. | en_US |
dc.contributor.committeeChair | Che, Hao | en_US |
dc.degree.department | Computer Science & Engineering | en_US |
dc.degree.discipline | Computer Science & Engineering | en_US |
dc.degree.grantor | University of Texas at Arlington | en_US |
dc.degree.level | doctoral | en_US |
dc.degree.name | Ph.D. | en_US |
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