Analytical Solutions Of Steady-state Heat Conduction In Multi-layer Stack Packaging

Abstract

Analytical models that can be utilized in modeling the steady-state temperature solutions of planar and 3D packaged integrated circuits are discussed. This mathematically-driven model will include solutions for uniform and non-uniform footprint die stack systems as well as planar flip chip packages. These analytically obtained temperature solutions will include the contribution of thermal resistance for both cases as well as perfect contact scenarios. The acquired solution will accommodate any kind of boundary conditions (first, second and third kind) on the top and bottom surfaces of the stack system with the sides being adiabatic. Furthermore, the algorithm developed will consider volumetric heat generation as well as heat source at any cross section within the model. Finally, the diffusion equation for heterogeneous layers is solved using the Galerkin-based integral approach. The latest development pertains to the analytical solutions of the steady-state heat conduction in stacked dies of an electronic chipset with or without TSV (Through Silicon Via) technology. TSVs are used as interconnections between different dies in vertical layers. Furthermore, the effect of thermal conductance between the constituents of the layers is considered.