Computational Analysis of Impact Loading on Wafer Level Chip Scale Packages Mounted on Printed Circuit Boards of Varying Thickness

Abstract

In the electronic industry one of the popular package is Chip Scale Package (CSP) due to its small form factor and low cost. To meet the need of new functionality and portability of the recent devices, CSPs’ have been most favorable choice for a long time. On the other hand, with the miniaturization process of these portable devices there is a growing risk of drop impact failure in day to day use. It’s not only the mechanical loading that is affecting the reliability of these devices but also thermal and thermo-mechanical loads are acting simultaneously. To analyze and ensure the reliability one should look through all the dimensions that can cause failure. The smaller the devices are getting they are becoming more prone to accidental drop and experience impact load, causing board interconnect failure by the repeatability of the drop occurrences. Therefore, the reliability of these products due to various loadings are being researched by taking multi-dimensional approach. To ensure product quality and to integrate more complicated functionality in these devices reliability test is very important. To meet the robust and quick production demand, one of the popular choices for manufacturers is to complement drop/shock testing with the aid of computational simulation using Finite Element Analysis (FEA). In this work, a comprehensive study has been carried out to investigate the effect of impact loading on the solder joints of Wafer Level Chip Scale Packages (WLCSP) component boards in environmental condition and also in elevated temperatures. In the environmental temperature the analysis approach was chosen as to observe the behavior of the solder joints failure during drop loading due to thickness and layer stack-ups difference in the Printed Circuit Boards (PCB). As drop test is dependent on modulus of elasticity and density of the materials they were experimentally determined for each board configuration. To understand the solder joint behavior under both thermal and mechanical load, drop test with respect to elevated temperature and using PCBs of varying thickness and layer stack-ups were simulated using Finite Element Method. The same WLCSP is used for different boards and subjected to drop test according to the JEDEC specifications [1]. To simulate the actual drop test modified Input G method, that is Direct Acceleration Input (DAI) method, was followed. The purpose of this study is to give an insight of how the impact loading is affected by the change of layer stack-ups and thicknesses of PCB mounted with small Wafer Level Chip Scale Packages (WCSPs) in the environmental and also in elevated temperatures. The comparison of the boards has been made to understand the effect of PCB layer stack-ups, thickness, and also temperature effect on the reliability of solder interconnects by considering the stress-strain generation that is induced in the PCBs during the drop test.