FPGA Prototyping For Fast And Efficient Verification Of ASIC H.264 Decoder

Abstract

To improve compression efficiency, recent video compression standards such as H.264 use complex algorithms and various modes that demand more computational power. Consumer electronics industry requires a low power, compact and cost-effective implementation of video codec for most of the products. ASIC implementation of these video codecs is a logical choice to meet these requirements. Functional verification of an ASIC implementation consumes a major part of design cycle time and lot of resources. Because of large design, various modes and options, functional verification of an ASIC H.264 video codec is a challenging, resource intensive and time consuming process. In this thesis an FPGA prototyping based functional verification technique has been suggested as fast and efficient alternative for functional verification of ASIC video codec. An FPGA prototyping of H.264 video codec has been performed for functional verification of ASIC video codec. Advantages and limitations have been elaborated with experimental results.